One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side or greater, resulting in crowding of the solder bumps on the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart at a pitch of typically about 150 um to 250 um.
A section of a typical conventional flip chip 26 is shown schematically in FIG. 1 and includes a solder bump 10 which is soldered to an under-bump metal (UBM) 11 provided on the continuous upper surface of a bump pad 14, typically rectangular in configuration, as shown in FIG. 1A, and partially covered by a passivation layer 12 which may be SiN or SiO2, for example. Some samples have a polyimide layer on the passivation layer 12 to resist the impact of alpha particles. A circular pad opening 13 in the passivation layer 12 exposes the bump pad 14, through which pad opening 13 the solder bump 10 extends. The bump pad 14 is surrounded by a dielectric layer 15 (which is typically covered by the passivation layer 12) such as an oxide in the chip 26. As further shown in FIG. 1, the bump pad 14 is provided in electrical contact with an upper conductive layer 16, which is separated from an underlying conductive layer 22 by an insulative layer 18. The conductive layers 16, 22 are disposed in electrical contact with each other through conductive vias 20 that extend through the insulative layers 18. The various insulative layers 18 and conductive layers 22 are sequentially deposited on a silicon chip substrate 24 throughout semiconductor fabrication, in conventional fashion. An RDL (re-distribution line, not shown) typically connects solder bumps 10 to an IO pad (not shown) which is provided typically at the edges of the flip chip 26.
After the solder bumps 10 are formed on the flip chip 26, the chip 26 is inverted (thus the term, “flip chip”) and the solder bumps 10 are bonded to electrical terminals in a substrate 28 such as a printed circuit board (PCB). As shown in FIG. 1B, the solder bumps 10 are typically provided on the flip chip 26 in a series of rows and columns. Frequently, an empty space 11 is left between adjacent solder bumps 10 in the rows and columns on the flip chip 26 due to the configuration of integrated circuits fabricated on the chip substrate 24 or other considerations.
After the solder bumps 10 are bonded to the PCB substrate 28, the flip chip 26 is subjected to a variety of tests such as, for example, bump shear tests and die shear tests, in which shear stress is applied to the flip chip 26 to determine the mechanical integrity of the electrical connections between the flip chip 26 and the bonded PCB substrate 28. The flip chip 26 may also be subjected to temperature tests, in which the flip chip 26 is subjected to cycling temperatures of typically about −55˜125 degrees C.
As shown in FIG. 1C, during high-temperature testing of the flip chip 26, the PCB substrate 28 expands at a higher rate than does the silicon chip substrate 24 and various insulative layers 18 and conductive layers 22 (FIG. 1) on which the solder bumps 10 are provided. This exerts considerable shear stress on the solder bumps 10, causing some of the solder bumps 10 to become detached or “lifted” from the dielectric layer 15 on the chip substrate 24. The highest magnitude of this temperature-induced shear stress is applied to those solder bumps 10 that are located adjacent to an empty space 11 between adjacent solder bumps 10 on the dielectric layer 15, as indicated by the arrows in FIG. 1B, since there exists no solder bump 10 in the empty space 11 to absorb and resist a portion of the shear stress applied to the flip chip 26. The temperature-induced shear stress is particularly acute for those solder bumps 10 that are located at the corners 26a and, to a somewhat lesser degree, at the edges 26b of the flip chip 26.
It has been found that providing an anchoring solder bump in an empty space between solder bumps on a flip chip significantly stabilizes the solder bumps located adjacent to the anchoring solder bump during temperature testing of the flip chip, since the anchoring solder bump provides an additional structure to resist and absorb the temperature-induced shear stress applied to the flip chip. This substantially prevents or reduces detachment or “lifting” of the solder bumps from the flip chip as the PCB substrate expands at a faster rate than the chip substrate and insulative and conductive layers thereon, resulting in a flip chip product having enhanced functional and structural integrity.
Accordingly, an object of the present invention is to provide novel methods suitable for reducing stress applied to solder bumps on a flip chip.
Another object of the present invention is to provide novel methods which are particularly effective in reducing stress applied to solder bumps on a flip chip during testing of the chip.
Still another object of the present invention is to provide novel methods which are particularly effective in reducing stress applied to solder bumps on a flip chip during high-temperature testing of the chip.
Yet another object of the present invention is to provide novel methods which may be used to reduce shear stress applied to solder bumps that are located adjacent to an empty space on a chip substrate.
A still further object of the present invention is to provide a novel method which includes providing an anchoring solder bump in an empty space on a chip substrate to reduce shear stress applied to solder bumps located adjacent to the empty space.
Yet another object of the present invention is to provide a novel method which includes providing an anchoring solder bump in an empty space on a chip substrate and providing a solder bridge between the anchoring solder bump and an adjacent solder bump on the chip substrate to reduce shear stress applied to solder bumps located adjacent to the empty space.